1. Field of the Invention
The present invention relates to a power-on reset circuit which produces a power-on reset signal at the time of power-on for the purpose of resetting individual sections of a semiconductor integrated circuit, as well as to a semiconductor device comprising the power-on reset circuit
2. Description of Related Art
A power-on reset circuit produces, during power-on, a power-on reset signal in response to an increase in the power supply voltage supplied to a semiconductor device for the purpose of initializing predetermined sections of a semiconductor integrated circuit. A conventional power-on reset circuit includes a power-on detection circuit such as that described in Japanese Patent Application Laid-open No. (Hei)5-168151. In such conventional power-on reset circuit, because of any of various technical reasons, such as recent advances in system complication or diversification or a reduction in a system voltage, if a rise in the power supply voltage occurring at power-on becomes very gentle, the power-on reset signal does not reliably assume a desired waveform, so that scheduled resetting or initialization of internal circuits cannot be performed reliably.
FIG. 19 shows the fundamental configuration of a power-on detection circuit described in, e.g., Japanese Patent Application Laid-open No. (Hei) 5-168151. The power-on reset circuit will be described more specifically by reference to this drawing.
FIG. 20 shows variations in the potential of individual nodes of a power-on reset circuit (hereinafter referred to simply as a "/POR circuit") in a case where a rise in a power supply voltage occurring at power-on is gentle such that the voltage takes about 5 ms to rise from the ground potential (0V) to the power supply voltage or line potential (5V).
In FIG. 19, reference numerals 1c, 2c, 3c, and 4c designate capacitors. Particularly, reference numeral 1c designates a capacitor for monitoring a rise in the line potential supply. Reference numerals i1, i2, i3, i4, and i5 designate inverter circuits, and a latch circuit 10 includes inverters i1 and i2. Reference numeral 20 designates a discharge circuit for discharging the electric charges stored in the capacitor 1c. The discharge circuit 20 comprises the inverter i5, a discharge transistor 1, a diode-connected transistor 2, and an N-channel transistor 3 connected between the ground potential and the gate of the discharge transistor 1. The inverter i1 comprises an N-channel transistor in and a P-channel transistor 1p; the inverter i2 comprises an N-channel transistor 2n and a P-channel transistor 2p; the inverter i3 comprises an N-channel transistor 3n and a P-channel transistor 3p; the inverter i4 comprises an N-channel transistor 4n and a P-channel transistor 4p; and the inverter i5 comprises an N-channel transistor 5n and a P-channel transistor 5p.
In FIG. 19, the output nodes of the individual inverters i1, i2, i3, i4, and is are taken as n1, n2, n3, n4, and n5, respectively, and the gate node of the discharge transistor 1 is taken as n20.
The operation of the power-on detection circuit will now be described. In FIG. 20, power is switched on at time t0, and the line potential gradually rises. Correspondingly, the potential of the output nodes of the individual inverters i1 to i5 and the potential of the /POR signal start increasing so as to follow a rise in the line potential. In this state, there is subtle continuity between the N-channel and P-channel transistors of each inverter, and a pass-through current flows through each inverter. The output potential may be at any potential level between the ground potential and the line potential and is very unstable. Under the influence of the inverters having their nodes connected together, the capacitors, and the load capacity of wiring patterns, a small time lag and a small potential difference arises in the output nodes. However, the potential of the output nodes rises so as to substantially follow the line potential. The monitoring capacitor 1c shown in FIG. 19 is comparatively higher in capacitance than the potential stabilizing capacitors 2c, 3c, and 4c. For this reason, when there is a lag in a rise in line potential, a great lag arises in a rise in the potential of the node n1, so that the charging of the node n2 is started by way of the P-channel transistor 2p of the inverter i2. Since the /POR signal line is routed to the individual internal circuits, the potential of the node n4 where the /POR signal appears is susceptible to wiring capacitance and resistance greater than those to which the other nodes are susceptible. Therefore, the /POR signal follows a rise in the line potential at a rate comparatively slower than that at which the other nodes follow.
At time t1, the potential of the /POR signal exceeds the threshold voltage of the N-channel transistor 3, thereby bringing the N-channel transistor 3 into conduction. The node n2 is brought to the ground potential, and the discharge transistor 1 is brought into a non-conducting state.
At time t2, the N-channel transistor in of the inverter i1 included in the latch circuit 10 is brought into conduction by means of a subtle balance of increase ratio between the potential of the node n1 and the potential of the node n2, thereby bringing the P-channel transistor 1p into a non-conducting state. Further, the N-channel transistor 2n of the inverter i2 is brought into a non-conducting state, thereby bringing the P-channel transistor 2p into conduction. Subsequently, regardless of the value of a rise in the line potential, the potential of the node n1 remains at an intermediate potential level and does not rise, because the N-channel transistor In of the inverter i1 is in conduction. In other words, the electric charges-which is being stored in the node n1 as a result of a rise in the line potential-is simultaneously discharged by means of the transistor 1n. As a result, the line potential is not monitored at all. In contrast, the potential of the node n2 follows a rise in the line potential by way of the P-channel transistor 2p. In FIG. 20, since the line potential finally achieves 5V, the intermediate potential assumes a value of 2.5V. However, it goes without saying that the intermediate potential may be lower or higher than 2.5V, depending on the size and configuration of transistors and capacitors or on wiring patterns.
At time t3, the N-channel transistor 3n of the inverter i3 is brought into conduction because of a rise in the potential of the node n2, thereby bringing the P-channel transistor 3p into a non-conducting state. As a result, the discharging of the electric charge stored in the node n3 is started, and the potential of the node n3 is gradually brought to the ground potential. In response to the gradual change in the potential, the N-channel transistor 4n of the inverter i4 is brought to a non-conducting state, and the P-channel transistor 4p of the same is brought to conduction. Accordingly, the /POR signal rises further so as to follow a rise in the line potential without being brought to the ground potential and is determined so as to equal the final power potential. Although the /POR signal is originally expected to remain in the ground potential until time t4 at which the power rises to 5V, the signal fails to satisfy the expected state.
As mentioned above, in the conventional /POR circuit, in a case where the potential of the power supply voltage at power-on is gentle, the latch circuits in the /POR circuit are held in a false state, thereby discharging electric charge which is being stored into a capacitor for monitoring a rise in line potential. As a result, the monitoring capacitor fails to fulfill its performance correctly, thereby hindering reliable detection of a power-on of a power supply voltage.
In such a case, the power-on of a power supply voltage cannot be detected, and the /POR signal assumes a waveform insufficient for reliable initializing the internal circuits.
Further, since the power-on of a power supply voltage is detected by means of only the monitoring capacitor, there can be detected only a rise in the potential of a portion of a power supply line. If the function of the monitoring capacitor becomes paralyzed or deteriorated because of process problems, the power-on of a power supply voltage cannot be detected correctly.